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| - 1 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target ddr sdram specification version 0.61
- 2 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target revision history version 0 (may, 1998) - first version for internal review version 0.1(june, 1998) - added x4 organization version 0.2(sep,1998) 1. added "issue prcharge command for all banks of the device" as the fourth step of power-up squence. 2. in power down mode timing diagram, nop condition is added to precharge power down exit. version 0.3(dec,1998) - added qfc function. - added dc current value - reduce i/o capacitance values version 0.4(feb,1999) -added ddr sdram history for reference(refer to the following page) -added low power version dc spec version 0.5(apr,1999) -revised following first showing for jedec standard - added dc target current based on new dc test condition version 0.6(july 1,1999) 1.modified binning policy from to -z (133mhz) -z (133mhz/266mbps@cl=2) -8 (125mhz) -y (133mhz/266mbps@cl=2.5) -0 (100mhz) -0 (100mhz/200mbps@cl=2) 2.modified the following ac spec values *1 : changed description method for the same functionality. this means no difference from the previous version. 3.changed the following ac parameter symbol from. to. output data access time from ck/ ck tdqck tac version 0.61(august 9,1999) - changed the some values of "write with auto precharge" table for different bank in page 30. from. to. -z -0 -z -y -0 tac +/- 0.75ns +/- 1ns +/- 0.75ns +/- 0.75ns +/- 0.8ns tdqsck +/- 0.75ns +/- 1ns +/- 0.75ns +/- 0.75ns +/- 0.8ns tdqsq +/- 0.5ns +/- 0.75ns +/- 0.5ns +/- 0.5ns +/- 0.6ns tds/tdh 0.5 ns 0.75 ns 0.5 ns 0.5 ns 0.6 ns tcdlr *1 2.5tck-tdqss 2.5tck-tdqss 1tck 1tck 1tck tpre *1 1tck +/- 0.75ns 1tck +/- 1ns 0.9/1.1 tck 0.9/1.1 tck 0.9/1.1 tck trpst *1 tck/2 +/- 0.75ns tck/2 +/- 1ns 0.4/0.6 tck 0.4/0.6 tck 0.4/0.6 tck thzq *1 tck/2 +/- 0.75ns tck/2 +/- 1ns +/- 0.75ns +/- 0.75ns +/-0.8ns asserted command for different bank 3 4 old new old new read legal illegal legal illegal read + ap *1 legal illegal legal illegal - 3 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target revision history - this revision history is for 64mb and only for reference in other density. version 0.5 (jun, 1997) - first version for external release - center aligned dq on reads and writes, 3.3v vdd/vddq, lvttl for command and sstl for dq, dqs, ck and dm. version 0.6 (sep. 1997) - changed to edge aligneddq on reads - add detailed discription for each functionality version 0.7 (jan. 1998) - power supply: 3.3v +10%,-5% power supply for device operation (vdd) 2.5v power supply for i/o interface (vddq) - interface: add sstl_2 for ck/dm (class i), dq/dqs(class ii) for km416h431t. * put two part numbers, km416h430t and km416h431t. - clock input: change to differential clock from single ended clock. * use ck, ck instead of clk. - package: change to 66pin tsop-ii, instead of 54pin tsop-ii - tdqss: change to 0.75 ~ 1.25 tck form 3ns ~ 1 tck. add tsdqs(dqs-in setup time) - in page 13, "dm can be ~" is modified to "dm must be ~". - tighten ac specs change ck/ck hign/low level width from 0.4(min)/0.6(max)tck to 0.45(min)/0.55(max)tck. -> better input clock duty ratio from differential clock. version 0.8 (feb. 1998) - correct pin rotation on pin 48 and 49 from 48-vref, 49-vss to 48-vss, 49-vref. version 0.9 (mar. 1998) - change power-up sequence . add emrs for dll enable/disable . change dll reset pin from a9 to a8 on mrs. - change speed range . add 133mhz (266mbps/pin), remove -12 (83mhz) - change output load circuit - change input capacitance - add a comment on read interrupting write timing: read command interrupting write can not be issued at the next clock edge of write command. - modify the simplified state diagram on page 24. version 0.91 (may, 1998) - changed part number from km416h430t/km416h431t to km416h4030t/km416h4031t - added the 66pin package dimension on page 30. - changed output load circuit 2 in page 29 - removed cl=1.5 - corrected typos - 4 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target contents revision history 2 ddr sdram ordering information 8 1. key features 9 1.1 features 9 1.2 operating frequencies 9 1.3 device information by organization 9 2. package pinout & dimension 10 2.1 package pintout 10 2.2 input/output function description 11 2.3 66 pin tsop(ii)/ms-024fc package physical dimension 12 3. functional description 13 3.1 simplified state diagram 13 3.2 basic functionality 14 3.2.1 power-up sequence 14 3.2.2 mode register definition 15 3.2.2.1 mode register set(mrs) 15 3.2.2.2 extended mode register set(emrs) 17 3.2.3 precharge 18 3.2.4 no operation(nop) & device deselect 18 3.2.5 row active 19 3.2.6 read bank 19 3.2.7 write bank 19 3.3 essential functionality for ddr sdram 20 3.3.1 burst read operation 20 3.3.2 burst write operation 21 3.3.3 read interrupted by a read 22 3.3.4 read interrupted by a write & burst stop 22 3.3.5 read interrupted by a precharge 23 3.3.6 write interrupted by a write 24 - 5 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.7 write interrupted by a read & dm 25 3.3.8 write interrupted by a precharge & dm 26 3.3.9 burst stop 27 3.3.10 dm masking 28 3.3.11 read with auto precharge 29 3.3.12 write with auto precharge 30 3.3.13 auto refresh & self refresh 31 3.3.14 power down 32 4. command truth table 33 5. functional truth table 34 6. absolute maximum rating 39 7. dc operating conditions & specifications 39 7.1 dc operating conditions 39 7.2 dc specifications 40 8. ac operating conditions & timming specification 41 8.1 ac operating conditions 41 8.2 ac timming parameters & specification 42 9. ac operating test conditions 44 10. input/output capacitance 44 11. ibis: i/v characteristics for input and output buffers 45 11.1 normal strength driver 45 11.2 half strength driver( will be included in the future) 47 12. qfc function 48 qfc definition 48 qfc timming on read operation 48 qfc timming on write operation with tdqssmax 49 qfc timming on write operation with tdqssmin 49 - 6 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target table 1 : operating frequency and dll jitter table 2. : column address configurtion table 3 : input/output function description table 4 : burst address ordering for burst length table 5 : bank selection for precharge by bank address bits table 6 : operating description when new command asserted while read with auto precharge is issued table 7 : operating description when new command asserted while write with auto precharge is issued table 8 : command truth table table 9-1 : functional truth table table 9-2 : functional truth table (contiued) table 9-3 : functional truth table (contiued) table 9-4 : functional truth table (contiued) table 9-5 : functional truth table (cotinued) table 10 : absolute maximum raings table 11 : dc operating condtion table 12 : dc specification table 13 : ac operating condition table 14 : ac timing parameters and specifications table 15 : ac operating test conditions table 16 : input/output capacitance table 17 : pull down and pull up current values list of tables 9 10 11 16 18 29 30 33 34 35 36 37 38 39 39 40 41 42 44 44 46 - 7 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target figure 1 : 128mb package pinout figure 2 : package dimension figure 3 :state digram figure 4 : power up and initialization sequence figure 5 : mode register set figure 6 : mode register set sequence figure 7 : extend mode register set figure 8 : bank activation command cycle timing figure 9 : burst read operation timing figure 10 : burst write operation timing figure 11 : read interrupted by a read timing figure 12 : read interrupted by a write and burst stop timing figure 13 : read interrupted by a precharge timing figure 14 : write interrupted by a write timing figure 15 : write interrupted by a read and dm timing figure 16 : write interrupted by a precharge and dm timing figure 17 : burst stop timing figure 18 : dm masking timing figure 19 : read with auto precharge timing figure 20 : write with auto precharge timing figure 21 : auto refresh timing figure 22 : self refresh timing figure 23 : power down entry and exit timing figure 24 : output load circuit (sstl_2) figure 25 : i / v characteristics for input/output buffers: pull-up(above) and pull-down(below) figure 26 : qfc timing on read operation figure 27 : qfc timing on write operation with tdqssmax figure 28 : qfc timing on write operation with tdqssmin list of figures 10 12 13 14 15 16 17 19 20 21 22 22 23 24 25 26 27 28 29 30 31 31 32 44 45 48 49 49 - 8 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target ? 0 mixed interface(lvttl & sstl_3 & 3.3v v ddq ) ? 1 sstl_2(2.5v v ddq ) ? t 66pin tsop-ii ? b bga ? c u - bga(csp) ? z 7.5ns, 133mhz@cl2 (266mbps/pin) ? y 7.5ns, 133mhz@cl2.5(266mbps/pin) ? 0 10ns, 100mhz @cl2(200mbps/pin) ? blank 1st gen. ? a 2nd gen. ? b 3rd gen. ? c 4th gen. ? 4 4m ? 8 8m ? 16 16m ? 32 32m ? 64 64m ? 12 128m ? 25 256m ? 51 512m ? 1g 1g ? 2g 2g ? 4g 4g ? h ddr sdram(3.3v v dd ) ? l ddr sdram(2.5v v dd ) ? 4 x4 ? 8 x8 ? 16 x16 ? 32 x32 ? g auto & self refresh ? f auto & self refresh with low power ? 3 4 banks ? 4 8 banks ? 4 dram ddr sdram ordering information km 4 xx l xx x x x x x - x x 1. samsung memory 2. device 3. organization 4. product & voltage(v dd ) 12. speed 11. power 10. package type 9. revision 5. depth 8. interface & voltage(v ddq ) 7. number of bank 1. samsung memory 2. device 3. organization 4. product & voltage(v dd ) 5. depth 7. number of bank 8. interface & voltage(v ddq ) 9. revision 10. package type 11. power 12. speed 6. refresh ? 0 64m/4k(15.6us) ? 1 32m/2k(15.6us) ? 2 128m/8k(15.6us) ? 3 64m/8k(7.8us) ? 4 128m/16k(7.8us) 6. refresh - 9 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? four banks operation ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? mrs cycle with address key programs -. read latency 2, 2.5 (clock) -. burst length (2, 4, 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive going edge of the system clock(ck) ? data i/o transactions on both edges of data strobe ? edge aligned data output, center aligned data input ? ldm,udm/dm for write masking only ? auto & self refresh ? 15.6us refresh interval ? maximum burst refresh cycle : 8 ? 66pin tsop ii package 1. key features 1.1 features 1.2 operating frequencies pc266a(-z) pc266b(-y) pc200(-0) speed 133mhz@cl2 133mhz@cl2.5 100mhz@cl2 dll jitter 0.75ns 0.75ns 0.8ns *cl : cas latency maximum operation frequency table 1. operating frequency and dll jitter 1.3 device information by organization density part no. operating freq. interface package 128mb km44l32031bt-g(f)z/y/0 133/133/100mhz sstl_2 66pin tsop ii km48l16031bt-g(f)z/y/0 km416l8031bt-g(f)z/y/0 - 10 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target v dd 1 66 pin tsop(ii) (400mil x 875mil) dq 0 2 v ddq 3 nc 4 dq 1 5 v ssq 6 nc 7 dq 2 8 v ddq 9 nc 10 dq 3 11 v ssq 12 ba 0 20 cs 19 ras 18 cas 17 we 16 nc 15 v ddq 14 nc 13 v dd 27 a 3 26 a 2 25 a 1 24 a 0 23 ap/a 10 22 ba 1 21 v ss 54 dq 7 53 v ssq 52 nc 51 dq 6 50 v ddq 49 nc 48 dq 5 47 v ssq 46 nc 45 dq 4 44 v ddq 43 a 11 35 36 cke 37 ck 38 dm 39 v ref 40 v ssq 41 nc 42 v ss 55 a 4 56 a 5 57 a 6 58 a 7 59 a 8 60 a 9 34 (0.65 mm pin pitch) 33 32 31 30 29 28 61 62 63 64 65 66 nc nc nc qfc /nc nc v dd nc dqs nc v ss ck nc nc 32mb x 4 16mb x 8 v ss nc v ssq nc dq 3 v ddq nc nc v ssq nc dq 2 v ddq a 11 cke ck dm v ref v ssq nc v ss a 4 a 5 a 6 a 7 a 8 a 9 nc dqs nc v ss ck nc nc v dd nc v ddq nc dq 0 v ssq nc nc v ddq nc dq 1 v ssq ba 0 cs ras cas we nc v ddq nc v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc nc nc qfc /nc nc v dd bank address ba0-ba1 row address a0-a11 auto precharge a10 ms-024fc organization column address 32mx4 a0-a9, a11 16mx8 a0-a9 8mx16 a0-a8 dm is internally loaded to match dq and dqs identically. 2.1 package pinout figure 1. 128mb package pinout table 2. column address configuration 1. package pinout & dimension v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq ba 0 cs ras cas we ldm v ddq dq 7 v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc ldqs nc qfc /nc nc v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq a 11 cke ck udm v ref v ssq dq 8 v ss a 4 a 5 a 6 a 7 a 8 a 9 nc udqs nc v ss ck nc nc 8mb x 16 - 11 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 2.2 input/output function description symbol type description ck, ck input clock : ck and ck are differential clock inputs. all address and control input signals are sam- pled on the positive edge of ck/negative edge of ck . output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ ck . cke input clock enable : cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke are disabled during power-down and self refresh modes, providing low standby power. cke will recognize an lvcmos low level prior to vref being stable on power-up. cs input chip select : cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks cs is considered part of the command code. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. ldm,(u)dm input input data mask : dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to matches the dq and dqs load- ing. for the x16, ldm corresponds to the data on dq0-dq7 ; udm correspons to the data on dq8-dq15. ba0, ba1 input bank addres inputs : ba0 and ba1 define to which bank active, read, write or pre- charge command is being applied. a [n : 0] input address inputs : provide the row address for active commands, the column address and auto precharge bit for read/write commands, to select one location out of the mem- ory array in the respective bank. a10 is sampled during a precharge command to deter- mine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). dq i/o data input/output : data bus ldqs,(u)dqs i/o data strobe : output with read data, input with write data. edge-aligned with read data, cen- tered in write data. used to capture write data. for the x16, ldqs corresponds to the data on dq0-dq7 ; udqs corresponds to the data on dq8-dq15. qfc output fet control : optional. output during every read and write access. can be used to control isolation switches on modules. nc - no connect : no internal electrical connection is present. v dd q supply dq power supply : +2.5v 0.2v. v ss q supply dq ground. v dd supply power supply : one of +3.3v 0.3v or +2.5v 0.2v (device specific). v ss supply ground. v ref input sstl_2 reference voltage. table 3. input/output function description - 12 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 2.3 66 pin tsop(ii)/ms-024fc package physical dimension units : millimeters 0.30 0.08 0.65typ (0.71) 22.22 0.10 0.125 ( 0 . 8 0 ) 1 0 . 1 6 0 . 1 0 0 ~8 #1 #33 #66 #34 (1.50) ( 1 . 5 0 ) 0.65 0.08 1 . 0 0 0 . 1 0 1 . 2 0 m a x ( 0 . 5 0 ) ( 0 . 5 0 ) ( 1 0 . 7 6 ) 1 1 . 7 6 0 . 2 0 (10 ) (10 ) +0.075 -0.035 ( 0 . 8 0 ) 0.10 max 0.075 max [ ] 0 . 0 5 m i n (10 ) (10 ) ( r 0 . 1 5 ) 0 . 2 1 0 0 . 0 5 0 . 6 6 5 0 . 0 5 ( r 0 . 1 5 ) ( 4 ) ( r 0 . 2 5 ) ( r 0 . 2 5 ) 0 . 4 5 ~ 0 . 7 5 0.25typ note 1. ( ) is reference 2. [ ] is ass ? y out quality figure 2. package dimension - 13 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3. functional description 3.1 simplified state diagram read self refresh auto refresh power down row active reada writea writea pre charge power on idle mode power down register set refs refsx refa mrs ckel ckeh act ckel ckeh write write writea pre pre power applied reada pre pre reada writea reada read read automatic sequence command sequence burst stop writea : write with autoprecharge reada : read with autoprecharge figure 3. state diagram - 14 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.2.1 power-up and initialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke at a low state(all other inputs may be undefined.) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. 2. start clock and maintain stable condition for a minimum of 200us. 3. the minimum of 200us after stable power and clock(ck, ck ), apply nop & take cke high. 4. issue precharge commands for all banks of the device. 5. issue emrs to enable dll.(to issue "dll enable" command, provide "low" to a0, "high" to ba0 and "low" to all of the rest address pins, a1~a11 and ba1) 6. issue a mode register set command for "dll reset". the additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide "high" to a8 and "low" to ba0) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command with low to a8 to initialize device operation. *1 every "dll enable" command resets dll. therefore sequence 6 can be skipped during power up. instead of it, the additional 200 cycles of clock input is required to lock the dll after enabling dll. *2 sequence of 6 & 7 is regardless of the order. power up & initialization sequence command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc min.200 cycle emrs mrs 2 clock min. dll reset *1 *2 *1 2 clock min. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ precharge all banks t rp ck ck 3.2 basic functionality figure 4. power up and initialization sequence - 15 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.2.2 mode register definition 3.2.2.1 mode register set(mrs) the mode register stores the data for controlling the various operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and various vendor specific options to make ddr sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for proper ddr sdram operation. the mode register is written by asserting low on cs , ras , cas , we and ba0(the ddr sdram should be in all bank pre- charge with cke already high prior to writing into the mode register). the states of address pins a0 ~ a11 in the same cycle as cs , ras , cas , we and ba0 going low are written in the mode register. two clock cycles are requested to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a0 ~ a2, addressing mode uses a3, cas latency(read latency from column address) uses a4 ~ a6. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal mrs operation. refer to the table for specific codes for various burst lengths, addressing modes and cas latencies. address bus cas latency a 6 a 5 a 4 latency 0 0 0 reserve d 0 0 1 reserve d 0 1 0 2 0 1 1 reserved 1 0 0 reserve d 1 0 1 reserved 1 1 0 2.5 1 1 1 reserve d burst length a 2 a 1 a 0 latency sequential interleave 0 0 0 reserve reserve 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve a 7 mode 0 normal 1 test a 3 burst type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. a 8 dll reset 0 no 1 yes mode register ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu tm cas latency bt burst length rfu dll 0 ba 0 a n ~ a 0 0 (existing)mrs cycle 1 extended funtions(emrs) figure 5. mode register set - 16 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target mode register set *1 : mrs can be issued only at all bank precharge state. *2 : minimum t rp is required to issue mrs command. command 2 0 1 5 3 4 8 6 7 t ck 2 clock min. precharge all banks mode register set t rp *2 *1 any command ck ck burst address ordering for burst length burst length starting address(a2, a1, a0) sequential mode interleave mode 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization, and upon returing to normal operation after having disabled the dll for the purpose of debug or evaluation (upon exiting self refresh mode, the dll is enabled automatically). any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. some vendors might also support a weak driver strength option, intended for lighter load and/or point-to-point environments. i-v curves for the normal drive strength and weak drive strength will be included in a future revision of this document. table 4. burst address ordering for burst length figure 6. mode register set sequence - 17 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.2.2.2 extended mode register set(emrs) the extended mode register stores the data for enabling or disabling dll, qfc and selecting output driver size. the default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling dll. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0 ~ a11 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on ba0 is used for emrs. all the other address pins except a0 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. address bus rfu rfu : must be set "0" extended mode register dll ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0 (existing)mrs cycle 1 extended funtions(emrs) qfc control 0 disable(default) 1 enable output driver impedence control 0 normal 1 weak qfc d.i.c figure 7. extend mode register set - 18 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.2.3 precharge 3.2.4 no operation(nop) & device deselect the precharge command is used to precharge or close a bank that has been activated. the precharge com- mand is issued when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank select addresses(ba0, ba1) are used to define which bank is precharged when the command is initiated. for write cycle, twr(min.) must be satisfied until the precharge command can be issued. after trp from the precharge, an active command to the same bank can be initiated. a10/ap ba1 ba0 precharge 0 0 0 bank a only 0 0 1 bank b only 0 1 0 bank c only 0 1 1 bank d only 1 x x all banks the device should be deselected by deactivating the cs signal. in this mode ddr sdram should ignore all the control inputs. the ddr sdrams are put in nop mode when cs is active and by deactivating ras , cas and we . for both deselect and nop the device should finish the current operation when this com- mand is issued. bank selection for precharge by bank address bits table 5. bank selection for precharge by bank address bits - 19 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.2.5 row active the bank activation command is issued by holding cas and we high with cs and ras low at the rising edge of the clock(ck). the ddr sdram has four independent banks, so two bank select addresses(ba0, ba1) are required. the bank activation command must be applied before any read or write operation is exe- cuted. the delay from the bank activation command to the first read or write command must meet or exceed the minimum of ras to cas delay time(trcd min). once a bank has been activated, it must be precharged before another bank activation command can be applied to the same bank. the minimum time interval between interleaved bank activation commands(bank a to bank b and vice versa) is the bank to bank delay time(trrd min). address command ras - cas delay( t rcd ) bank activation command cycle ( cas latency = 2) bank a row addr. bank a col. addr. bank a activate write a with auto nop precharge ras - ras delay time( t rrd ) bank b row addr. bank a row. addr. bank b activate bank a activate nop row cycle time( t rc ) tn tn+1 tn+2 2 0 1 : don t care ck ck 3.2.6 read bank 3.2.7 write bank this command is used after the row activate command to initiate the burst read of data. the read command is initiated by activating ras , cs , cas , and deasserting we at the same clock sampling(rising) edge as described in the command truth table. the length of the burst and the cas latency time will be determined by the values programmed during the mrs command. this command is used after the row activate command to initiate the burst write of data. the write com- mand is initiated by activating ras , cs , cas , and we at the same clock sampling(rising) edge as described in the command truth table. the length of the burst will be determined by the values programmed during the mrs command. figure 8. bank activation command cycle timing - 20 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.1 burst read operation burst read operation in ddr sdram is in the same manner as the current sdram such that the burst read command is issued by asserting cs and cas low while holding ras and we high at the rising edge of the clock(ck) after trcd from the bank activation. the address inputs (a0~a9) determine the starting address for the burst. the mode register sets type of burst(sequential or interleave) and burst length(2, 4, 8). the first output data is available after the cas latency from the read command, and the consecutive data are pre- sented on the falling and rising edge of data strobe(dqs) adopted by ddr sdram until the burst length is completed. command < burst length=4, cas latency= 2, 2.5 > read a nop nop nop nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 dout 2 dout 3 dqs dq s cas latency=2.5 dout 0 dout 1 dout 2 dout 3 2 0 1 5 3 4 8 6 7 t rpre t rpst ck ck 3.3 essential functionality for ddr sdram the essential functionality that is required for the ddr sdram device is described in this chapter figure 9. burst read operation timing - 21 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.2 burst write operation the burst write command is issued by having cs , cas , and we low while holding ras high at the rising edge of the clock(ck). the address inputs determine the starting column address. there is no write latency relative to dqs required for burst write cycle. the first data of a burst write cycle must be applied on the dq pins tds(data-in setup time) prior to data strobe edge enabled after tdqss from the rising edge of the clock(ck) that the write command is issued. the remaining data inputs must be supplied on each subsequent falling and rising edge of data strobe until the burst length is completed. when the burst has been finished, any additional data supplied to the dq pins will be ignored. figure 10. burst write operation timing 1. the soecific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown (dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. (refer to ac parameter table in page 42) *1 command < burst length=4 > nop write a nop nop nop writeb nop nop nop dqs dq s din 3 din 0 din 1 din 2 t dqssmax 2 0 1 5 3 4 8 6 7 t wpres*1 ck ck din 3 din 0 din 1 din 2 - 22 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.3 read interrupted by a read a burst read can be interrupted before completion of the burst by new read command of any bank. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied. at this point the data from the interrupting read command appears. read to read interval is minimum 1 clock. command < burst length=4, cas latency=2 > read a read b nop nop nop nop nop nop nop dqs dq s cas latency=2 d out a 0 d out a 1 d out b 0 d out b 1 d out b 2 d out b 3 2 0 1 5 3 4 8 6 7 ck ck 3.3.4 read interrupted by a write & burst stop to interrupt a burst read with a write command, burst stop command must be asserted to avoid data conten- tion on the i/o bus by placing the dq ? s (output drivers) in a high impedance state. to insure the dq ? s are tri- stated one cycle before the beginning the write operation, burst stop command must be applied at least 2 clock cycles for cl=2 and at least 3 clock cycles for cl=2.5 before the write command. command < burst length=4, cas latency=2 > read burst stop nop write nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 din 0 din 1 din 2 din 3 2 0 1 5 3 4 8 6 7 ck ck the following functionality establishes how a write command may interrupt a read burst. 1. for write commands interrupting a read burst, a burst terminate command is required to stop the read burst and tristate the dq bus prior to valid input write data. once the burst terminate command has been issued, the minimum delay to a write command = ru(cl) [cl is the cas latency and ru means round up to the nearest integer]. 2. it is illegal for a write command to interrupt a read with autoprecharge command. figure 11. read interrupted by a read timing figure 12. read interrupted by a write and burst stop timing. - 23 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.5 read interrupted by a precharge a burst read operation can be interrupted by precharge of the same bank. the minimum 1 clock is required for the read to precharge intervals. a precharge command to output disable latency is equivalent to the cas latency. command < burst length=8, cas latency=2 > read nop precharge nop nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 dout 2 dout 3 interrupted by precharge 2 0 1 5 3 4 8 6 7 dout 4 dout 5 dout 6 dout 7 1t ck ck ck when a burst read command is issued to a ddr sdram, a precharge command may be issued to the same bank before the read burst is complete. the following functionality determines when a precharge command may be given during a read burst and when a new bank activate command may be issued to the same bank. 1. for the earliest possible precharge command without interrupting a read burst, the precharge command may be given on the rising clock edge which is cl clock cycles before the end of the read burst where cl is the cas latency. a new bank activate command may be issued to the same bank after trp (ras precharge time). 2. when a precharge command interrupts a read burst operation, the precharge command may be given on the rising clock edge which is cl clock cycles before the last data from the interrupted read burst where cl is the cas latency. once the last data word has been output, the output buffers are tristated. a new bank activate command may be issued to the same bank after trp. 3. for a read with autoprecharge command, a new bank activate command may be issued to the same bank after trp where trp begins on the rising clock edge which is cl clock cycles before the end of the read burst where cl is the cas latency. during read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external precharge command would initiate a precharge operation without interrupting the read burst as described in 1 above. 4. for all cases above, trp is an analog delay that needs to be converted into clock cycles. the number of clock cycles between a precharge command and a new bank activate command to the same bank equals trp/tck (where tck is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. (note that rounding to x.5 is not possible since the precharge and bank activate commands can only be given on a rising clock edge). in all cases, a precharge operation cannot be initiated unless tras(min) [minimum bank activate to precharge time] has been satisfied. this includes read with autoprecharge commands where tras(min) must still be satisfied such that a read with autoprecharge command has the same timing as a read command followed by the earliest possible precharge command which does not interrupt the burst. figure 13. read interrupted by a precharge timing - 24 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.6 write interrupted by a write a burst write can be interrupted before completion of the burst by a new write command, with the only restric- tion that the interval that separates the commands must be at least one clock cycle. when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. command < burst length=4 > nop write a write b nop nop nop nop nop nop dqs dq s din a 0 din a 1 din b 0 din b 1 din b 2 din b 3 1t ck 2 0 1 5 3 4 8 6 7 ck ck figure 14. write interrupted by a write timing - 25 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.7 write interrupted by a read & dm a burst write can be interrupted by a read command of any bank. the dq ? s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. when the read command is registered, any residual data from the burst write cycle must be masked by dm. the delay from the last data to read command (tcdlr) is required to avoid the data contention dram inside. data that are presented on the dq pins before the read command is initiated will actually be written to the memory. read command interrupting write can not be issued at the next clock edge of that of write command. command < burst length=8, cas latency=2 > nop write nop nop read nop nop nop nop dqs dq s din 0 din 1 din 2 din 3 din 4 din 5 dout 0 dout 1 dout 2 din 6 din 7 t cdlr cas latency=2 t dqssmax dqs dq s t cdlr cas latency=2 t dqssmin din 7 din 0 din 1 din 2 din 3 din 4 din 5 din 6 d m do dout 0 dout 1 dout 2 do 2 0 1 5 3 4 8 6 7 t wpres t wpres ck ck the following function established how a read command may interrupt a write burst and which input data is not written into the memory. 1. for read commands interrupting a write burst, the minimum write to read command delay is 2 clock cycles. the case where the write to read delay is 1 clock cycle is disallowed 2. for read commands interrupting a write burst, the dm pin must be used to mask the input data words whcich immediately precede the interrupting read operation and the input data word which immediately follows the interrupting read operation 3. for all cases of a read interrupting a write, the dq and dqs buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the ddr sdram drives them during a read operation. 4. if input write data is masked by the read command, the dqs input is ignored by the ddr sdram figure 15. write interrupted by a read and dm timing - 26 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.8 write interrupted by a precharge & dm a burst write operation can be interrupted before completion of the burst by a precharge of the same bank. random column access is allowed. a write recovery time(twr) is required from the last data to precharge command. when precharge command is asserted, any residual data from the burst write cycle must be masked by dm. command < burst length=8 > nop write a nop nop precharge nop nop nop writeb dqs dq s dina 0 dina 1 dina 2 dina 3 dina 4 dina 5 dinb 0 dina 6 dina 7 t wr dqs dq s t dqssmin dina 7 dina 0 dina 1 dina 2 dina 3 dina 4 dina 5 dina 6 d m dinb 0 dinb 1 t dqssmax 2 0 1 5 3 4 8 6 7 ck ck precharge timing for write operations in drams requires enough time to allow ?write recovery? which is the time required by a dram core to properly store a full ?0? or ?1? level before a precharge operation. for ddr sdram, a timing parameter, twr, is used to indicate the required amount of time between the last valid write operation and a precharge command to the same bank. the precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. inside the sdram, the data path is eventually synchronized with the address path by switching clock domains from the data strobe clock domain to the input clock domain. this makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation, i.e., the input clock domain. twr starts on the rising clock edge after the last possible dqs edge that strobed in the last valid data and ends on the rising clock edge that strobes in the precharge command. 1. for the earliest possible precharge command following a write burst without interrupting the burst, the minimum time for write recovery is defined by twr. 2. when a precharge command interrupts a write burst operation, the data mask pin, dm, is used to mask input data during the time between the last valid write data and the rising clock edge on which the precharge command is given. during this time, the dqs input is still required to strobe in the state of dm. the minimum time for write recovery is defined by twr. figure 16. write interrupted by a precharge and dm timing - 27 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3. for a write with autoprecharge command, a new bank activate command may be issued to the same bank after twr+trp where twr+trp starts on the falling dqs edge that strobed in the last valid data and ends on the rising clock edge that strobes in the bank activate command. during write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external precharge command without interrupting the write burst as described in 1 above. 4. in all cases, a precharge operation cannot be initiated unless tras(min) [minimum bank activate to precharge time] has been satisfied. this includes write with autoprecharge commands where tras(min) must still be satisfied such that a write with autoprecharge command has the same timing as a write command followed by the earliest possible precharge command which does not interrupt the burst. 3.3.9 burst stop the burst stop command is initiated by having ras and cas high with cs and we low at the rising edge of the clock(ck). the burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been completed. when the burst stop command is issued dur- ing a burst read cycle, the pair of data and dqs(data strobe) go to a high impedance state after a delay which is equal to the cas latency set in the mode register. the burst stop command, however, is not supported dur- ing a write burst operation. command < burst length=4, cas latency= 2, 2.5 > read a burst stop nop nop nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 dqs dq s cas latency=2.5 the burst ends after a delay equal to the cas latency. dout 0 dout 1 2 0 1 5 3 4 8 6 7 ck ck the burst stop command is a mandatory feature for ddr sdrams. the following functionality is required: 1. the bst command may only be issued on the rising edge of the input clock, ck. 2. bst is only a valid command during read bursts. 3. bst during a write burst is undefined and shall not be used. 4. bst applies to all burst lengths. 5. bst is an undefined command during read with autoprecharge and shall not be used. figure 17. burst stop timing - 28 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.10 dm masking the ddr sdram has a data mask function that can be used in conjunction with data write cycle, not read cycle. when the data mask is activated (dm high) during write operation, ddr sdram does not accept the corresponding data.(dm to data-mask latency is zero). dm must be issued at the rising or falling edge of data strobe. command < burst length=8 > write nop nop nop nop nop nop nop nop dqs dq s din 0 din 1 din 2 din 3 t dqss dm din 4 din 5 din 6 din7 masked by dm=h 2 0 1 5 3 4 8 6 7 ck ck 6. when terminating a burst read command, the bst command must be issued l bst (?bst latency?) clock cycles before the clock edge at which the output buffers are tristated, where l bst equals the cas latency for read operations. this is shown in previous page figure with examples for cas latency (cl) of 1.5, 2, 2.5, 3 and 3.5 (only selected cas latencies are required by the ddr sdram standards, the others are optional). 7. when the burst terminates, the dq and dqs pins are tristated. the bst command is not byte controllable and applies to all bits in the dq data word and the(all) dqs pin(s). figure 18. dm masking timing - 29 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target command < burst length=4, cas latency= 2, 2.5> bank a nop read a nop nop nop nop nop nop dqs dq s cas latency=2 dout 0 dout 1 dout 2 dout 3 active auto precharge * bank can be reactivated at the t rp completion of precharge begin auto-precharge dqs dq s cas latency=2.5 dout 0 dout 1 dout 2 dout 3 when the read with auto precharge command is issued, new command can be asserted at 3,4 and 5 respectively as follows, asserted command for same bank for different bank 3 4 5 3 4 5 read read + no ap *1 read+ no ap illegal legal legal legal read+ap read + ap read + ap illegal legal legal legal active illegal illegal illegal legal legal legal precharge legal legal illegal legal legal legal *1 : ap = auto precharge 2 0 1 5 3 4 8 6 7 t ras(min.) ck ck 3.3.11 read with auto precharge if a read with auto-precharge command is initiated, the ddr sdram automatically enters the precharge operation bl/2 clock later from a read with auto-precharge command when tras(min) is satisfied. if not, the start point of precharge operation will be delayed until tras(min) is satisfied. once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time(trp) has been satisfied. figure 19. read with auto precharge timing table 6. operating description when new command asserted while read with auto precharge is issued - 30 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.12 write with auto precharge if a10 is high when write command is issued , the write with auto-precharge function is performed. any new command to the same bank should not be issued until the internal precharge is completed. the internal pre- charge begins after keeping twr(min). command < burst length=4 > bank a nop write a nop nop nop nop nop nop dqs dq s din 0 din 1 din 2 din 3 active auto precharge * bank can be reactivated at completion of t rp t wr t rp internal precharge start 2 0 1 5 3 4 8 6 7 ck ck figure 20. write with auto precharge timing asserted command for same bank for different bank 3 4 5 6 7 8 3 4 5 6 7 write write+ no ap *1 write+ no ap write+ no ap illegal illegal illegal legal legal legal legal legal write+ ap write+ ap write+ ap write+ ap illegal illegal illegal legal legal legal legal legal read illegal read+no ap+dm *2 read+no ap+dm read+ no ap read+ no ap illegal illegal illegal legal legal legal read+ap illegal read + ap+dm read + ap+dm read + ap read + ap illegal illegal illegal legal legal legal active illegal illegal illegal illegal illegal illegal legal legal legal legal legal precharge illegal illegal illegal illegal illegal illegal legal legal legal legal legal *1 : ap = auto precharge *2 : dm : refer to " 3.3.7 write interrupted by a read & dm " in page 25. burst length = 4 table 7. operating description when new command asserted while write with auto precharge is issued - 31 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.13 auto refresh & self refresh auto refresh command cke pre t rp t rfc auto = high refresh cmd an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the ris- ing edge of the clock(ck). all banks must be precharged and idle for trp(min) before the auto refresh com- mand is applied. no control of the external address pins is required once this cycle has started because of the internal address counter. when the refresh cycle has completed, all banks will be in the idle state. a delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the trfc(min). ~ ~ ~ ~ ~ ~ ck ck self refresh a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock(ck). once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. during the self refresh operation, all inputs except cke are ignored. the clock is internally disabled during self refresh operation to reduce power consumption. the self refresh is exited by supplying stable clock input before returning cke high, asserting deselect or nop command and then asserting cke high for longer than txsr for locking of dll. command cke t xsa self refresh ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ck ck ~ ~ ~ ~ ~ ~ read t xsr figure 21. auto refresh timing figure 22. self refresh timing active - 32 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 3.3.14 power down cke precharge active active read power down exit active power down entry power entry down precharge command ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ck ck the power down mode is entered when cke is low and exited when cke is high. once the power down mode is initiated, all of the receiver circuits except clock, cke and dll circuit tree are gated off to reduce power consumption. the all banks should be in idle state prior to entering the precharge power down mode and cke should be set high at least 1tck+tis prior to row active command . during power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period(tref) of the device. figure 23. power down entry and exit timing - 33 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 4. command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dm ba 0,1 a 10 /ap a 11, a 9 ~ a 0 note register extended mrs h x l l l l x op code 1, 2 register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~a 9 ) 4 auto precharge enable h 4 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~a 9 ) 4 auto precharge enable h 4, 6 burst stop h x l h h l x x 7 precharge bank selection h x l l h l x v l x all banks x h 5 active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dm h x v x 8 no op eration (nop) : not defined h x h x x x x x 9 l h h h 9 1. op code : operand code. a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2.emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram. table 8. command truth table - 34 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 5. functional truth table current state cs ras cas we address command action precharge standby l h h l x burst stop illegal*2 l h l x ba, ca, a 10 read/write illegal*2 l l h h ba, ra active bank active, latch ra l l h l ba, a 10 pre/prea illegal *4 l l l h x refresh auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 active standby l h h l x burst stop nop l h l h ba, ca, a 10 read/reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a 10 write/writea begin write, latch ca, determine auto-precharge l l h h ba, ra active bank active/illegal*2 l l h l ba, a 10 pre/prea precharge/precharge all l l l h x refresh illegal l l l l op-code, mode-add mrs illegal read l h h l x burst stop terminate burst l h l h ba, ca, a 10 read/reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a 10 write/writea illegal l l h h ba, ra active bank active/illegal*2 l l h l ba, a 10 pre/prea terminate burst, precharge l l l h x refresh illegal l l l l op-code, mode-add mrs illegal table 9-1. functional truth table - 35 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target current state cs ras cas we address command action write l h h l x burst stop illegal l h l h ba, ca, a 10 read/reada terminate burst with dm=high, latch ca, begin read, deter- mine auto-precharge*3 l h l l ba, ca, a 10 write/writea terminate burst, latch ca, begin new write, determine auto-precharge*3 l l h h ba, ra active bank active/illegal*2 l l h l ba, a 10 pre/prea terminate burst with dm=high, precharge l l l h x refresh illegal l l l l op-code, mode-add mrs illegal read with auto precharge *6 (reada) l h h l x burst stop illegal l h l h ba, ca, a 10 read/reada *6 l h l l ba, ca, a 10 write/writea illegal l l h h ba, ra active *6 l l h l ba, a 10 pre/prea *6 l l l h x refresh illegal l l l l op-code, mode-add mrs illegal write with auto recharge *7 (writea) l h h l x burst stop illegal l h l h ba, ca, a 10 read/reada *7 l h l l ba, ca, a 10 write/writea *7 l l h h ba, ra active *7 l l h l ba, a 10 pre/prea *7 l l l h x refresh illegal l l l l op-code, mode-add mrs illegal table 9-2. functional truth table - 36 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target current state cs ras cas we address command action precharg- ing (during trp) l h h l x burst stop illegal*2 l h l x ba, ca, a 10 read/write illegal*2 l l h h ba, ra active illegal*2 l l h l ba, a 10 pre/prea nop*4(idle after t rp ) l l l h x refresh illegal l l l l op-code, mode-add mrs illegal row activating (from row active to trcd) l h h l x burst stop illegal*2 l h l x ba, ca, a 10 read/write illegal*2 l l h h ba, ra active illegal*2 l l h l ba, a 10 pre/prea illegal*2 l l l h x refresh illegal l l l l op-code, mode-add mrs illegal write recovering (during twr or tcdlr) l h h l x burst stop illegal*2 l h l h ba, ca, a 10 read illegal*2 l h l l ba, ca, a 10 write write l l h h ba, ra active illegal*2 l l h l ba, a 10 pre/prea illegal*2 l l l h x refresh illegal l l l l op-code, mode-add mrs illegal table 9-3. functional truth table - 37 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target current state cs ras cas we address command action re- freshing l h h l x burst stop illegal l h l x ba, ca, a 10 read/write illegal l l h h ba, ra active illegal l l h l ba, a 10 pre/prea illegal l l l h x refresh illegal l l l l op-code, mode-add mrs illegal mode register setting l h h l x burst stop illegal l h l x ba, ca, a 10 read/write illegal l l h h ba, ra active illegal l l h l ba, a 10 pre/prea illegal l l l h x refresh illegal l l l l op-code, mode-add mrs illegal table 9-4. functional truth table - 38 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target abbreviations : h=high level, l=low level, x=don t care note : 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state ; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around and write recovery requirements. 4. nop to bank precharging or in idle sate. may precharge bank indicated by ba. 5. illegal if any bank is not idle. 6. refer to "3.3.11 read with auto precharge" in page 29 for detailed information. 7. refer to "3.3.12 write with auto precharge" in page 30 for detailed information. 8 . cke low to high transition will re-enable ck, ck and other inputs asynchronously. a minimum setup time must be satisfied before issuing any command other than exit. 9. power-down and self-refresh can be entered only from all bank idle state. illegal = device operation and/or data integrity are not guaranteed. current state cke n-1 cke n cs ras cas we add action self- refreshing *8 l h h x x x x exit self-refresh l h l h h h x exit self-refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x noperation(maintain self-refresh) power down l h x x x x x exit power down(idle after t pdex ) l l x x x x x noperation(maintain power down) all banks idle *9 h h x x x x x refer to function true table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state=power down any state other than listed above h h x x x x x refer to function truth table table 9-5. functional truth table - 39 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 6. absolute maximum rating 7. dc operating conditions & specifications 7.1 dc operating conditions parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v voltage on v ddq supply relative to v ss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommend operation condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 3.3v) v dd 3.0 3.6 v supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref 1.15 1.35 v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.18 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.18 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v input leakage current i i -5 5 ua 3 output leakage current i oz -5 5 ua output high current (v out = 1.95v) i oh -15.2 ma output low current (v out = 0.35v) i ol 15.2 ma notes 1. v ref is expected to be equal to 0.5*v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to- peak noise on v ref may not exceed 2% of the dc value 2.v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . table 10. absolute maximum ratings table 11. dc operating condition - 40 of 60 - rev. 0.0 apr. '99 pc 200/266 ddr sdram 128mb ddr sdram table 12. dc specifications parameter symbol test condition version unit note -z -y -0 precharge power-down standby current idd2p cke vil(max), tck=tck(min), all banks idle 25 ma idle standby current idd2n cke 3 vih(min), cs 3 vih(min), tck=tck(min) 45 ma active power-down standby current idd3p all banks idle, cke vil(max), tck=tck(min) 40 ma active standby current idd3n one bank; active-precharge, trc=tras(max), tck=tck(min) 60 ma auto refresh current idd5 trc = trfc(min) 200 165 ma 2 self refresh current idd6 cke 0.2v 2.5 ma parameter symbol test condition version unit note -z -y -0 operating current (one bank active) idd0 trc = trc(min) tck=tck(min) active-precharge t.b.d t.b.d t.b.d ma 1 operating current (one bank active) idd1 burst=2 trc = trc(min), cl=2.5 i out =0ma, active-read-precharge 135 135 115 ma operating current(read) idd4r burst=2, cl=2.5, tck=tck(min), i out =0ma 170 170 145 ma 1 operating current(write) idd4w burst=2, cl=2.5, tck=tck(min) 130 130 110 ma 1 parameter symbol test condition version unit note -z -y -0 operating current (one bank active) idd0 trc = trc(min) tck=tck(min) active-precharge t.b.d t.b.d t.b.d ma 1 operating current (one bank active) idd1 burst=2 trc = trc(min), cl=2.5 i out =0ma, active-read-precharge 125 125 105 ma operating current(read) idd4r burst=2, cl=2.5, tck=tck(min), i out =0ma 150 150 125 ma 1 operating current(write) idd4w burst=2, cl=2.5, tck=tck(min) 115 115 95 ma 1 16mx8 128mb(common) note 1.measured with outputs open. 2. refresh period is 64ms. parameter symbol test condition version unit note -z -y -0 operating current (one bank active) idd0 trc = trc(min) tck=tck(min) active-precharge t.b.d t.b.d t.b.d ma 1 operating current (one bank active) idd1 burst=2 trc = trc(min), cl=2.5 i out =0ma, active-read-precharge 145 140 125 ma operating current(read) idd4r burst=2, cl=2.5, tck=tck(min), i out =0ma 200 200 175 ma 1 operating current(write) idd4w burst=2, cl=2.5, tck=tck(min) 150 150 130 ma 1 8mx16 7.1 dc specifications 32mx4 - 41 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 8. ac operating conditions & timming specification 8.1 ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.35 v input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.35 v input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 note 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. table 13. ac operating conditions - 42 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target parameter symbol - z(pc266@cl=2) - y(pc266@cl=2.5) - 0(pc200@cl=2) unit note min max min max min max row cycle time trc 65 65 70 ns refresh row cycle time trfc 75 75 80 ns row active time tras 45 12k 48 12k 48 12k ns ras to cas delay trcd 20 20 20 ns row precharge time trp 20 20 20 ns row active to row active delay trrd 15 15 15 ns write recovery time twr 2 2 2 tck last data in to read command tcdlr 1 1 1 tck last data in to write command tcdlw 0 0 0 tck col. address to col. address delay tccd 1 1 1 tck clock cycle time cl=2.0 tck 7.5 15 10 15 10 15 ns cl=2.5 7 15 7.5 15 8 15 ns clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ ck tac -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to ouput data edge tdqsq -0.5 +0.5 -0.5 +0.5 -0.6 +0.6 ns read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck data out high impedence time from ck/ ck thzq -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 2 ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 ns 3 dqs-in hold time twpreh 0.25 0.25 0.25 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time tis 1.1 1.1 1.2 ns address and control input hold time tih 1.1 1.1 1.2 ns mode register set cycle time tmrd 15 15 16 ns dq & dm setup time to dqs tds 0.5 0.5 0.6 ns dq & dm hold time to dqs tdh 0.5 0.5 0.6 ns dq & dm input pulse width tdipw 1.75 1.75 2 ns power down exit time tpdex 10 10 10 ns exit self refresh to write command txsw 95 116 ns 8.2 ac timming parameters & specifications - 43 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target . 1. maximum burst refresh of 8 2. thzq transitions occurs in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. 3. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 4. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. parameter symbol pc266a pc266b pc200 unit note min max min max min max exit self refresh to bank active command txsa 75 75 80 ns exit self refresh to read command txsr 200 200 200 cycle refresh interval time 64mb, 128mb tref 15.6 15.6 15.6 us 1 256mb 7.8 7.8 7.8 us 1 output dqs valid window tdv 0.35 0.35 0.35 tck dqs write postamble time twpst 0.25 0.25 0.25 tck 4 auto precharge write recovery + precharge time tdal 35 35 35 ns table 14. ac timing parameters and specifications - 44 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 9. ac operating test conditions (v dd =2.5/3.3v, v ddq =2.5v, t a = 0 to 70 c) parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate 1.0 v/ns input levels(v ih /v il ) v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit 10. input/output capacitance (v dd =2.5, v ddq =2.5v, t a = 25 c , f=1mhz) parameter symbol min max unit input capacitance (a 0 ~ a 11 , ba 0 ~ ba 1, cke, cs , ras , cas , we ) c in1 2.5 3.5 pf input capacitance( ck, ck ) c in2 2.5 3.5 pf data & dqs input/output capacitance(dq 0 ~dq 15 ) c out 4.0 5.5 pf input capacitance(dm) c in3 4.0 5.5 pf table 15. ac operating test conditions table 16. input/output capacitance figure 24. output load circuit (sstl_2) output z0=50 w c load =30pf v ref =0.5*v ddq r t =50 w v tt =0.5*v ddq - 45 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 11. ibis: i/v characteristics for input and output buffers 1. the nominal pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of figure a. 2. the full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the v-i curve of below figure. maximum nominal high nominal low minumum vout(v) i o u t ( m a ) 3. the nominal pullup v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of below figure. 4. the full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of below figrue vout(v) i o u t ( m a ) 5. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to vddq/2 minimum nominal low nominal high maximum figure 25. i/v characteristics for input/output buffers:pull up(above) and pull down(below) 11.1 normal strength driver - 46 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target temperature (tjunction) typical 50 c minimum 0 c maximum 0 c vdd/vddq normal 2.5v minimum 2.3v maximum 2.7v the adove characteristics are specied under best, worst and normal process variation/conditions pulldown current (ma) pullup current (ma) voltage (v) normal low normal high minimum maximum normal low normal high minimum maximum 0.1 5.7 6.4 4.3 8.3 -5.8 -7.2 -4.3 -8.6 0.2 11.5 12.7 8.7 16.5 -11.5 -13.7 -8.7 -17.0 0.3 17.1 19.0 13.0 24.4 -17.1 -20.0 -13.0 -25.3 0.4 22.7 25.1 17.4 32.0 -22.6 -26.1 -17.4 -33.6 0.5 28.1 31.1 21.7 39.4 -28.1 -32.2 -21.7 -41.7 0.6 32.6 36.9 26.1 46.6 -32.4 -38.2 -26.1 -49.6 0.7 37.2 41.7 30.4 53.6 -35.9 -44.2 -30.4 -57.5 0.8 41.2 47.0 34.7 59.6 -38.8 -50.1 -34.0 -65.2 0.9 44.8 52.1 37.4 65.9 -41.3 -56.0 -36.0 -72.9 1.0 48.4 56.9 40.2 72.0 -43.4 -61.8 -36.5 -80.4 1.1 51.0 61.5 42.3 77.8 -45.1 -67.5 -36.8 -87.7 1.2 53.0 65.9 43.6 83.3 -46.4 -73.2 -37.0 -94.9 1.3 54.6 70.0 44.4 88.5 -47.2 -78.9 -37.2 -102.0 1.4 55.9 74.0 44.7 93.5 -47.6 -84.6 -37.4 -109.0 1.5 56.7 77.6 45.0 97.9 -47.8 -90.1 -37.6 -116.0 1.6 57.1 81.0 45.3 102.3 -48.1 -95.6 -37.8 -123.0 1.7 57.5 84.1 45.7 105.8 -48.2 -101.0 -37.9 -129.0 1.8 58.0 87.0 46.1 109.3 -48.4 -106.0 -38.0 -136.0 1.9 58.5 89.9 46.3 112.8 -48.6 -112.0 -38.1 -142.0 2.0 59.0 91.7 46.6 116.3 -48.7 -117.0 -38.2 -148.0 2.1 59.3 93.5 46.8 119.3 -48.9 -122.0 -38.3 -154.0 2.2 59.7 95.2 47.0 122.2 -49.1 -127.0 -38.4 -160.0 2.3 60.2 96.1 47.1 124.9 -49.2 -132.0 -38.5 -166.0 2.4 60.5 97.0 47.2 127.4 -49.3 -137.0 -38.6 -171.0 2.5 60.9 97.9 47.4 129.5 -49.5 -142.0 -38.7 -177.0 table 17. pull down and pull up current values - 47 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 11.2 half strength driver the half strength driver ibis will be included in the future. - 48 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target 12. qfc function when drive low on reads coincident with the start of dqs, this dram output signal says that one cycle later there will be the first valid dqs output and returned to hi-z after this finishing a burst operation. it is also driven low shortly after a write command is received and returned to hi-z shortly after the last data strobe transition is received. whenever the device is in standby, the signal is hi-z. dqs is intended to enable an external data switch. qfc can be enabled or disabled through emrs control . qfc timming on read operation qfc on reads is enabled coincident with the start of dqs preamble, and disabled coincident with the end of dqs postamble command 2 0 1 5 3 4 8 6 7 read dout 0 dout 1 hi-z dqs dq?s qfc t qcs t qch cl = 2, bl = 2 ck ck qfc definition figure 26. qfc timing on read operation - 49 of 63 - rev. 0.61 august 9. '99 128mb ddr sdram target qfc timming on write operation with tdqssmax qfc on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last dqs-in low going edge. 2 0 1 5 3 4 8 6 7 hi-z dqs@tdqssmax qfc t qcsw t qchw dout 0 dout 1 bl = 2 write dq?s@tdqssmax command ck ck qfc timming on write operation with tdqssmin dqs@tdqssmin dq?s@tdqssmin qfc on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last dqs-in low going edge. 2 0 1 5 3 4 8 6 7 hi-z qfc t qcsw t qchw dout 0 dout 1 bl = 2 write command ck ck figure 27. : qfc timing on write operation with tdqssmax figure 28. : qfc timing on write operation with tdqssmax |
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